Circuitos fisicamente não clonáveis para sistemas digitais seguros usando tecnologias híbridas: eletrónica impressa e CMOS

This proposal is focused on the research and development of low cost PUF IDs that can be used in authentication, encryption key generation, and identity functions, which can be employed in document validation, authentication seals and also in all sorts of internet-of-things (IoT) related applications requiring authentication procedures. To further improve PUFs’ reliability, randomness, energy-efficiency and stability the project will combine the best of two quite different technologies namely, printed-electronics and silicon CMOS. On the one hand, the required static entropy will be extracted mainly from mismatch variation of an innovative matrix of passive metal contacts (VIAS) directly printed on sustainable substrates. On the other hand, the digitization and the most sophisticated error-correction coding (ECC) digital techniques will be used, to remove and correct all existing unstable bits and to deal with possible temperature and ageing effects. This will be done in a dedicated and ultra-small (< 1.5 x 1.5 mm2) CMOS integrated-circuit (chip), which can be easily hidden into the document itself. This hybrid combination of large-area electronics with deep nanoscale CMOS will provide fully reliable keys and unique IDs. In this project we have five major sub-objectives (SO): SO1 – Explore new (combined) sources of static entropy mainly from mismatch variation in passive metal contacts devices printed on flexible substrates and based on a passive-like squared matrix, with n rows and n columns, separated by a low-k insulator. SO2 – Use mostly-passive incremental delta-sigma modulators to implement digitization and stabilization simultaneously. Using this circuit, for a static entropy, it is possible to obtain a low BER bit stream, due to intrinsic negative feedback of Delta Sigma modulators architectures. S03 - Use of an energy-harvesting system (for energy collection and storage) constituted by an antenna (fabricated together with the entropy generator in the flexible substrate) and a power-management unit (DC-DC conversion to provide the adequate supply voltage). Therefore, the chip will be self-powered. SO4 – Explore new computing paradigms to embed artificial intelligence and machine learning in the PUF circuits. Machine learning-based approaches will be further studied as to model BER and further decrease it to lower the burden on ECC circuits. We will also explore the combination of deep Learning algorithms for data encryption (reducing execution time and power dissipation). SO5 – Design and build a final demonstrator of a complete PUF system, using an on-chip RF energy harvesting system, targeting flexible and secure stamps for documents authentication and IoT applications. At the end of this project and with the development of new hardware primitives (PUFs and TRNGs) Europe will be able to conceptualize and implement a design flow to sustain the trust chain for silicon produced in a non-trusted environment (e.g. Asia and specially in China). Thus, Europe will keep design capabilities, intellectual property, and control of the trust chain.