Unidade Configurável de Processamento Neuronal para Inteligência Embebida

Embedded Deep learning is progressively entering in many application domains permitting the introduction of artificial intelligence in seemingly everything. The resilience is caused by the difficulty in running accurate models in embedded systems with dissimilar characteristics. The hardware constraints of embedded devices are quite challenging for deploying deep neural networks. Unless further progress in computing architectures and models is achieved, the revolution of intelligent IoT will stagnate. The proposed project's main objective is to contribute with a computing system for embedded AI addressing the following research and development questions: (1) how to design a configurable custom hardware architecture that can manage the complexity and heterogeneity of convolutional neural network models; (2) how to improve the computational and energy efficiency of custom-designed architectures; (3) how to reduce the energy and computing requirements of CNN models; (4) how to integrate the NPU in a System-on-Chip (SoC) solution. The project focuses on the following points to achieve this objective: - Architecture design: designing a hardware computing solution with a high peak performance is not the approach for embedded AI. Most existing NPU solutions provide an architecture with a very high peak performance, but a low computing and energy efficiency. This low efficiency is more evident when running more complex and heterogeneous models. Embedded AI requires computational efficiency to be useful. This project is focused on achieving this. The idea is to consider a high-level hardware configurability that allows the adaptation of the dataflow and arithmetic units to the target model. Energy is a major constraint of embedded computing. Therefore, the project will focus on reducing energy and power consumption with special attention to the utilization of external memory, a major energy consumer; - Model design: In general, deep learning models are designed for a particular task to improve accuracy without considering the computing costs of algorithmic techniques and model size. In general, an exponential increase in complexity is observed for a marginal improvement in accuracy. This is not the correct approach when designing for embedded AI, where the tradeoff between accuracy and computing matters. Models for embedded AI must be designed or redesigned constrained by computing, memory, and energy requirements. Also, the efficiency of a model optimization or redesign depends on the target architecture. So, the model design cannot be dissociated from the architecture. Tradeoffs must be explored considering the hardware implementation. A model design framework for embedded AI based on known deep learning frameworks is proposed in this project. Contrary to previous works that dissociate the model design from the architecture design, the proposed framework will integrate the hardware characteristics in the model design framework, as well as energy and memory aspects; - System-on-chip for NPU integration. The NPU will be integrated into a System-on-Chip to work as an autonomous system with memory and controlled by an embedded processor. These approaches are ambitious and will advance the state of the art in this field. Their research and development will contribute to the introduction of autonomous Intelligent systems.